Memory device

ABSTRACT

A memory device operable to receive an input signal and to generate a corresponding data bearing output signal in response. The device includes a series of circuit stages operable to be triggered by the input signal at a first stage of the series, thereby causing a sequential triggering of stages along the series to a last stage of the series to generate the output signal, the data represented in time durations taken for each stage in the series to trigger a subsequent stage in the series. Sequential triggering of the stages generates a data bearing output signal for output from the device. The device can be modified to repetitively output the data in response to the input signal. Moreover, the device can be adapted to provide a delay before repeating the data, thereby coping with contention when several of the devices are operating within range of one another.

The present invention relates to a memory device operable to outputinformation stored therein in response to being interrogated; inparticular, but not exclusively, it relates to a memory device operableto output data stored therein in response to being remotely interrogatedusing electromagnetic radiation.

Conventional transponding devices susceptible to remote interrogation,for example transponder tags, can operate passively to reflect radiationincident thereupon or, alternatively, can operate actively to receiveradiation and emit corresponding response radiation. It is known foractive transponding devices to encode response radiation emittedtherefrom with information stored in the devices, for example encodingthe response radiation with one or more signature codes uniquelyidentifying each device.

Conventional active transponding devices suffer from a number ofdrawbacks, namely:

-   -   (a) they require an internal source of power to function, for        example a miniature cell; and    -   (b) they require relatively complex circuits when configured to        respond with information such as a signature code unique        thereto, for example by using dedicated microcontrollers and        associated memory operable to store signature information.

The inventor has appreciated that it is feasible to fabricate a memorydevice capable of actively responding with a memorized signature code,namely with information stored therein, without needing to use complexcomponents such as microcontrollers. The transponder device can therebybe made relatively inexpensive.

According to a first aspect of the invention, there is provided a memorydevice operable to receive an input signal and to generate acorresponding data bearing output signal in response, the deviceincluding a series of circuit stages operable to be triggered by theinput signal at a first stage of the series thereby causing a sequentialtriggering of stages along the series to a last stage of the series togenerate the output signal, the data represented in time durations takenfor each stage in the series to trigger a subsequent stage in theseries.

The invention provides the advantage that the series of stages iscapable of bearing information and reading out the information in asequential manner when triggered.

Advantageously, the stages are arranged such that each stageincorporates an input connected to a preceding stage in the series andan output connected to a successive stage in the series, each stageoperable to exhibit an associated signal propagation delay therethroughfrom its input to its output, the propagation delays of the stagesrepresenting the data. Representing information in propagation delays ofthe stages provides the benefit that the propagation delays are manifestas durations between a series of current pulses when reading informationfrom the stages.

Conveniently, each stage incorporates a resistor and a capacitor fordetermining its propagation delay. Use of the resistor and capacitor todetermine the propagation delay provides a benefit that laser trimmingcan be applied to adjust their resistances and capacitances forprogramming data into the stages.

Preferably, each capacitor includes liquid crystal material as adielectric for the capacitor, the material being optically modifiablefor setting the propagation delay of its associated stage. Use of liquidcrystal material enables capacitances of the capacitors to be adjustedby laser irradiation. If the material is bistatic, it becomes possibleto reprogram the stages by further laser irradiation thereof

In some applications of the device, it is desirable for the device torepeat information stored therein to allow an apparatus interrogating itmore than one opportunity to receive information programmed into thedevice. Thus, advantageously, the series of stages includes a feedbackpath therearound linking the first stage to the last stage, the feedbackpath operable to cause the series to repetitively output its data duringa period where the input signal is applied to the device.

A problem of contention can arise when several devices according to thefirst aspect of the invention are operated within range of aninterrogating apparatus. It is thus desirable to interrupt output ofdata from each device to provide the apparatus with an opportunity ofreceiving information from individual devices without interference fromthe others. Thus, beneficially, the device incorporates controllingmeans for interrupting repetition of the data in response to the inputsignal received.

Preferably, each stage is operable to switch its respective outputbetween binary states. Moreover, conveniently, each stage is operable toexhibit a Schmitt-trigger characteristic from its input to its output.Use of binary states and Schmitt-trigger characteristics enables thedevice to provide a more determinate output therefrom.

In order to support remote interrogation, the device advantageouslyfurther includes coupling means:

-   -   (a) for receiving input radiation and for generating the input        signal in response; and    -   (b) for receiving the output signal and emitting output        radiation from the means in response.

The coupling means enables the device to be remotely interrogated.Remote interrogation makes the device useful for attachment to productsor packages, for example for enabling information regarding the productsor packages to be ascertained by interrogating the device.

The coupling means beneficially comprises a magnetically coupled loopantenna for receiving the input radiation and emitting the outputradiation. Use of a loop antenna is convenient when the device is in theform of a planar card where the antenna is implemented as a loopedconductive foil track printed or etched onto the card.

In order to circumvent a need for a local power supply in the device,for example a mercury button cell, the device advantageously includesconverting means for converting a portion of the input signal into anelectrical signal for powering and triggering the stages, the stagesoperable to present a variable load to the electrical signal, therebymodulating a portion of the input radiation reflected from the couplingmeans, the portion of the input radiation corresponding to the outputradiation. The converting means enables the device to be powered fromradiation received thereat. Conveniently, the converting means comprisesrectifying means for rectifying part of the input radiation to generatea unipolar signal and charge storing means for filtering the unipolarsignal to generate the electrical signal.

In order to enable the device to be conveniently fabricated usingconventional microfabrication techniques, the stages of the devicepreferably incorporate FETs, the stages coupled together by sharing asingle FET drain-source channel extending along the series.

Alternatively, when the device is used in environments wheresemiconductors would be unsuitable, for example at high temperatures inexcess of 200° C. or where intense ionising radiation is experiencedwhich would cause semiconductor devices to avalanche or latch-up, eachstage advantageously incorporates a piezoelectric bimorph switchingstructure operable to deflect in response to a signal at the input ofthe stage and thereby generate a signal at the output of the stage fortriggering a subsequent stage of the series.

The device according to the first aspect of the invention can beincorporated into portable transponder tags, for example personalidentity tags which are personnel wearable.

According to a second aspect of the present invention, there is providedan apparatus operable to interrogate a device according to the firstaspect of the invention and operable to receive sequentially outputinformation stored therein.

According to a third aspect of the present invention, there is provideda method of outputting information stored in a device according to thefirst aspect, the method including the steps of:

-   -   (a) receiving an input signal at the device;    -   (b) applying the input signal to trigger the first stage in the        series, thereby causing a sequential triggering of stages along        the series from the first stage to the last stage in the series,        the sequential triggering generating a corresponding output        signal, the output signal conveying data represented in time        durations taken for each stage in the series to trigger a        subsequent stage in the series; and    -   (c) outputting the output signal.

Embodiments of the invention will now be described, by way of exampleonly, with reference to the following drawings in which:

FIG. 1 is a schematic illustration of a first embodiment of a memorydevice according to the invention, the embodiment including an antenna,a rectification unit and a memory unit;

FIG. 2 is a schematic illustration of a first memory circuit for use inthe memory device in FIG. 1;

FIG. 3 is a graph of a current load presented by the circuit of FIG. 2when triggered in the device of FIG. 1;

FIG. 4 is a schematic illustration of a second memory circuit for use inthe memory device in FIG. 1;

FIG. 5 is an illustration of a third memory circuit for the use in thememory device in FIG. 1, the third circuit incorporating a single FETchannel spanning stages of the circuit;

FIG. 6 is an illustration of a fourth memory circuit for use in thedevice in FIG. 1, the fourth circuit incorporating a Schmitt gate ineach stage of the circuit;

FIG. 7 is an illustration of a fifth memory circuit for use in thedevice in FIG. 1, the fifth circuit incorporating a Schmitt gate in eachstage of the circuit and a feedback path to cause repetitive triggeringof the stages;

FIG. 8 is a schematic illustration of a second embodiment of a memorydevice according to the invention, the embodiment including an antenna,a rectification unit and a memory unit;

FIG. 9 is an illustration of a sixth memory circuit for use in thedevice in FIG. 8, the sixth circuit incorporating a Schmitt gate in eachstage of the circuit, a feedback path to cause repetitive triggering ofthe stages, and further additional components to interrupt repetitivetriggering of the stages to counteract contention;

FIG. 10 is an illustration of a seventh memory circuit for use in thedevice in FIG. 1, the seventh circuit incorporating bimorph switchingelements;

FIG. 11 is a schematic illustration of a spatial implementation of thebimorph elements in FIG. 10;

FIG. 12 is a schematic illustration of a third embodiment of a memorydevice according to the invention, the embodiment including a patchantenna for operating at a frequency in the order of 1 GHz;

FIG. 13 is a schematic illustration of interrogating equipment forinterrogating the device in FIG. 12; and

FIG. 14 is a circuit diagram of a memory unit of the memory device inFIG. 12, the memory unit adapted for coping with multiple devicecontention.

Referring to FIG. 1, there is shown indicated by 10 a first embodimentof a memory device according to the invention together with aninterrogation apparatus indicated by 20 operable to interrogate thedevice 10.

The device 10 comprises a substrate 30, for example a plastic card ofphysical dimensions similar to an ISO standard credit card having alength of 85 mm, a width of 54 mm and a thickness of 0.8 mm. The device10 further incorporates a loop antenna indicated by 40 implemented inthe form of a conductive metal foil track formed onto a major surface ofthe substrate 30. The antenna 40 is connected to a rectification unitindicated by 50, the unit 50 including a tuning capacitor 52, ahigh-frequency rectifier diode 54 and a storage capacitor 56; the unit50 is accommodated into a first recess formed into the major surface.The capacitor 52 is arranged to resonate with an inductance provided bythe antenna 40 at an operating frequency of the device 10, namely at afrequency f₀. The device 10 further comprises a memory unit indicated by60 accommodated into a second recess formed into the major surface. Onaccount of the units 50, 60 being accommodated in recesses formed intothe substrate 30, the major surface of the substrate 30 is planarwithout components projecting outwardly therefrom.

The apparatus 20 comprises a loop antenna indicated by 100 connected toa tuning capacitor C_(T) indicated by 110 and also to an electronicmodule 120 operable to drive the antenna 100. The capacitor C_(T) isoperable to resonate with an inductance provided by the antenna 100 atthe frequency f₀.

Interactive operation of the apparatus 20 and the device 10 will now bedescribed with reference to FIG. 1. The apparatus 20 and the device 10are mutually aligned along an axis A–B so that the antennae 100, 40 aremutually electromagnetically coupled. The module 120 generates a signalat the frequency f₀ which it injects to the antenna 100 which emitscorresponding electromagnetic radiation. The radiation is received atthe antenna 40 to generate a received signal thereat. The receivedsignal is rectified at the unit 50 to provide a direct current (d.c.)potential difference across the storage capacitor 56, the potentialdifference existing between a positive line V+ and a negative line V−provided to the memory unit 60. The memory unit 60 is triggered intooperation by the potential difference and provides a time varyingcurrent load to the unit 50. This varying current load affects theamount of power transferred from the apparatus 20 to the device 10. Themodule 120 is operable to sense power flow therefrom to the device 10and thereby sense the time varying current load.

The memory unit 60 is operable to provide the time varying load to theunit 50 according to data stored in the unit 60. Thus, the module 120 byway of the time varying load is capable of sensing the data stored inthe unit 60.

The apparatus 20 and the device 10 can be used in a range ofapplications. For example, the device 10 can be affixed to packaging andinterrogated by the apparatus 20, thereby providing for automaticidentification of the packaging. Alternatively, the device 10 can beworn as an identity tag and the apparatus 20 can be used to control anaccess door, the device 10 therefore useable to enable authorised accessonly to regions accessible through the door.

The memory unit 60 will now be described in further detail withreference to FIG. 2. The memory unit 60 comprises a first circuitindicated by 200. The circuit 200 is connected to the positive line V+and the negative line V− provided from the rectification unit 50.Moreover, the circuit 200 includes a cascaded series of stages ofmutually identical configuration; only stages 1 to 4 are shown in thediagram although the circuit 200 includes further stages after stage 4.Each stage incorporates a switch 210, a timing resistor 220 and a timingcapacitor 230. Each switch comprises three terminals A, B, C and isoperable such that its terminals A and B are mutually isolated in anon-conducting state unless a potential at its terminal C is less than athreshold amount V_(T) negative with respect to its terminal A in whichcase the terminals A and B are connected together to render the switchin a conducting state.

Each stage includes an input connected to its switch 210 terminal A andto a first end of its resistor 220. Each stage has an output which isconnected to the terminal B of its switch 210. A second end of theresistor is connected to the terminal C of the switch 210 and to a firstelectrode of the capacitor 230. A second electrode of the capacitor 230is connected to the line V−.

Stage 1 has its input connected to the line V+. For stage 2 andsuccessive stages, each stage has its input connected to the output ofits preceding stage in the cascaded series, and its output connected toits succeeding stage in the series.

Operation of the circuit 200 will now be described with reference toFIG. 2. Initially there is no potential difference between the lines V+and V−. Radiation emitted from the apparatus 20 is received by thedevice 10 causing a potential difference to be generated from a time T₁onwards across the lines V+ and V−; the potential difference is greaterthan the threshold amount V_(T). Initially at the time T₁ andimmediately therebefore, the capacitors 230 are in a discharged statethereby forcing the terminals C of the switches 210 to a potential ofthe line V− at the time T₁.

At the time T₁, stage 1 is not in a conducting state because its switch210 a terminal A is at a potential of the line V+ whereas its terminal Cis at a potential of the line V−. The capacitor 230 a from time T₁onwards charges through the resistor 220 a and eventually attains apotential of the amount V_(T) negative with respect to the line V+whereat the switch 210 a switches to a conducting state therebyconnecting stage 2 via stage 1 to the line V+.

When the line V+ is connected via stage 1 to stage 2 of the circuit 200,the terminal C of stage 2 switch 210 b is at a potential of the line V−whereas the terminal A of the switch 210 b is at a potential of the lineV+ rendering the switch 210 b in a non-conducting state. The capacitor230 b charges through the resistor 220 b until a potential at the switch210 b terminal C is within the amount V_(T) less than the switch 210 bterminal A whereat the switch 210 b switches to a conducting statethereby connecting stage 3 to the line V+ via stages 2 and 1. Subsequentstages in the sequence become sequentially connected through theirpreceding stages to the line V+ until all the stages in the series areconnected to the line V+. As each stage of the series becomes connectedvia its preceding stages to the line V+, a current I_(L) taken by thecircuit 200 from the line V+ fluctuates in a exponentially decayingpulsed manner as the capacitors 230 of the stages become charged throughtheir respective resistors 220 from the line V+.

The circuit 200 can be modified to incorporate in a range of two or morestages as required depending upon the complexity of information to bestored in the circuit 200. The resistors 220 and the capacitors 230 canhave their values selected so that each stage has a mutually differentpropagation delay for switching from a non-conducting state to aconducting state; the propagation delays thereby capable of conveyinginformation to the apparatus 20 which indirectly senses pulses in thecurrent I_(L).

Referring now to FIG. 3, there is shown a graph indicated by 300 of acurrent load presented by the circuit 200 when triggered by theapparatus 20. The graph 300 includes a horizontal axis 310 indicatingthe passage of time from left to right, and two vertical axes 320, 330corresponding to input radiation strength received at the antenna 40 andto the current I_(L) absorbed by the circuit 200 respectively. Curves340, 350 are associated with the axes 330, 320 respectively.

Prior to the time T₁, there is zero input radiation received at thedevice 10 from the apparatus 20; as a consequence, the circuit 200 doesnot demand current prior to the time T₁. At the time T₁, the apparatus20 commences to emit radiation which is received at the antenna 40 at apower level R_(I) as illustrated by the curve 350. The radiation issustained after the time T₁.

At the time T₁ and shortly thereafter, the capacitor 56 charges up andresults in a non-abrupt leading edge to a current peak 400 correspondingto current flowing through the resistor 220 a charging the capacitor 230a The current peak 400 falls exponentially during a propagation delayD_(I) through stage 1 until a potential across the capacitor 230 a iswithin a difference of the amount V_(T) from the line V+ potential at atime T₂.

At the time T₂, the switch 210 a switches to a conducting state causinga second current peak 410 corresponding to the capacitor 230 b chargingthrough the resistor 220 b. The current peak 410 decays exponentiallyduring a propagation delay D₂ through stage 2 until a potential acrossthe capacitor 230 b is within a difference of the amount V_(T) from theline V+ potential at a time T₃.

At the time T₃, the switch 210 b switches to a conducting state causinga third current peak 420 corresponding to the capacitor 230 c chargingthrough the resistor 220 c. The current peak 420 decays exponentiallyduring a propagation delay D₃ through stage 3 until a potential acrossthe capacitor 230 d is within a difference of the amount V_(T) from theline V+ potential at a time T₄.

At the time T₄, the switch 210 c switches to a conducting state causinga fourth current peak 430 corresponding to the capacitor 230 d chargingthrough the resistor 220 d. The current peak 430 decays exponentiallyduring a propagation delay D₄ through stage 4 until a potential across acapacitor 230 d of stage 5 (not shown) is within a difference of theamount V_(T) from the line V+ potential at a time T₅.

A sequential triggering process continues to further stages of thecircuit 200 in a similar manner as described for stages 2 to 4. Bycontrolling the propagation delays D₁ to D₄ and those of further stages,information is conveyed in the current demand of the circuit 200 whichis sensed at the apparatus 20 as information.

Durations of the delays D₁ to D₄ will be influenced by the intensity ofthe input radiation received at the antenna 40 after the time T₁. If theintensity of the input radiation is increased, the durations D₁ to D₄will also increase because the potential difference between the linesV+, V− will be increased relative to the threshold amount V_(T).Conversely, if the potential difference between the lines V+, V− is lessthan the amount V_(T), the circuit 200 will not function correctly toread out data therefrom.

Referring now to FIG. 4, there is shown a second circuit indicated by500 for incorporation into the unit 60 in substitution for the circuit200. The circuit 500 incorporates more than three stages although onlystages 1 to 3 are shown. Each stage includes a p-channel metal-oxidesemiconductor field effect transistor (MOSFET) TR together with acapacitor C and a resistor R, for example stage 1 includes a MOSFET TR1,a resistor R₁ and a capacitor C₁. Each stage has an input which isconnected to a source electrode (S) of its MOSFET TR and to a firstelectrode of its capacitor C. A second electrode of the capacitor C isconnected to a gate electrode (G) of the MOSFET TR and to a firstelectrode of the resistor R. A second electrode of the resistor R isconnected to the line V−. Moreover, each stage has an output which isconnected to a drain electrode (D) of its MOSFET TR.

The line V+ is connected to the input of stage 1. The output of stage 1is connected to the input of stage 2. The output of stage 2 is connectedto the input of stage 3, and so on.

The stages in the circuit 500 are identical except that the resistor Rand capacitor C of each stage are selected to impart mutually differentpropagation delays for the stages, thereby recording information in thepropagation delays of the stages.

Operation of the circuit 500 will now be described with reference toFIG. 4. Radiation is emitted from the apparatus 20 which is received atthe device 10 and then rectified thereat to generate a potentialdifference between the lines V+, V− at a time T_(A). The MOSFETS TR areat the time T_(A) and immediately therebefore in a non-conducting statebecause their associated capacitors C are all discharged.

After the time T_(A), the capacitor C₁ charges through its associatedresistor R₁ until the gate electrode G of TR1 is more negative relativeto the source electrode S of TR1 by an amount corresponding to athreshold voltage of TR1 whereat, at a time T_(B), the MOSFET TR1commences to conduct between its source (S) and drain (D) electrodes toconnect stage 2 via stage 1 to the line V+.

The capacitor C₂ of stage 2 then commences to charge through itsassociated resistor R₂ until a potential across the capacitor C₂ exceedsan amount corresponding to a threshold voltage of TR2 whereat, at a timeT_(C), the MOSFET TR2 commences to conduct between its source (S) anddrain (D) electrodes to connect stage 3 via stages 1 and 2 to the lineV+.

The capacitor C₃ of stage 3 then commences to charge through itsassociated resistor R₃ until a potential across the capacitor C₃ exceedsan amount corresponding to a threshold voltage of TR3 whereat, at a timeT_(D), the MOSFET TR3 commences to conduct between its source (S) anddrain (D) electrodes to connect stage 4 (not shown) via stages 1 to 3 tothe line V+, and so on.

An exponentially decaying current pulse is extracted from the line V+each time a successive stage of the circuit 500 is triggered by itspreceding stage.

The circuit 500 has the advantage that it can be microfabricated and theresistors R and capacitors C trimmed by laser to encode data into thecircuit 500 represented as the propagation delays of the stages of thecircuit 500 which are manifest in time durations between current pulsesextracted from the line V+.

When microfabricating the circuit 500, it is convenient to implement itin the form of a third circuit illustrated in FIG. 5 and indicated by600. The MOSFETs of the circuit 500 are implemented with their channelsfabricated as a continuous channel region 610 in FIG. 5. The sourceelectrodes (S) in the circuit 500 are implemented in the third circuit600 as connection regions, for example a region 620. The gateselectrodes (G) in the circuit 500 are implemented as insulated gateelectrodes, for example a gate electrode 630, along the continuouschannel region 610. As in the circuit 500, each stage of the circuit 600incorporates an associated resistor and capacitor for determiningpropagation delay therethrough, for example stage 1 in the circuit 600includes an associated resistor 640 and an associated capacitor 650 fordetermining propagation delay therethrough. The resistors can beimplemented as lightly doped polysilicon tracking and the capacitors canbe incorporated as junction capacitances to a substrate of the thirdcircuit 600 which is maintained at the line V− potential; thepolysilicon tracks are thereby exposed and accessible to laser trimmingfor programming data into the third circuit 600.

The circuits 200, 500, 600 suffer the disadvantage that stages far alongthe series of these circuits remote from stage 1 are fed throughnumerous preceding stages. There arises thereby a maximum limit to thenumber of stages that can be incorporated into the circuits 200, 500,600 because each stage has a voltage drop there across when in aconducting state, hence stages far along the series are subjected toless than the potential of the line V+ in operation. In order to addressthis maximum limit, an alternative fourth circuit is shown in

FIG. 6 and indicated by 700, the circuit 700 capable of beingincorporated into the unit 60 of the device 10.

In FIG. 6, the circuit 700 comprises eight stages 1 to 8 configured inseries, for example a stage 1 and a stage 5 indicated by 710 and 720respectively. The stages 1 to 8 are identical except that they areprogrammed to exhibit mutually different signal propagation delaystherethrough. Stage 1 710 comprises a Schmitt gate 750, a resistor 760and a capacitor 770. Stage 1 includes an input connected to an input ofthe gate 750. Moreover, stage 1 includes an output connected to a firstelectrode of the capacitor 770 and a first end of the resistor 760. Asecond end of the resistor 760 is connected to an output of the gate 750and a second electrode of the capacitor 770 is connected to the line V−.The gate 750 also incorporates a positive supply terminal and a negativesupply terminal which are connected to the lines V+, V− respectively.

The input of stage 1 710 is connected to a first end of a resistor 780and to a first electrode of a capacitor 790. A second electrode of thecapacitor 790 and a second end of the resistor 780 are connected to thelines V−, V+ respectively. The output of stage 1 is connected to aninput of stage 2. An output of stage 2 is connected to an input of stage3 and so on until stage 8 whose output is not connected to furtherstages.

The gates in the stages 1 to 8 are operable to provide a binary outputsubstantially at potentials of the lines V−, V+ and also exhibit ahysteresis characteristic at their inputs, the characteristic known toone skilled in the art of logic circuit design.

Operation of the circuit 700 incorporated into the device 10 andinterrogated by the apparatus 20 will now be described. Initially, theapparatus 20 is not emitting radiation; the capacitor 790 and thecapacitors in the stages 1 to 8 are all discharged. At a time T_(a), theapparatus 20 commences to emit radiation which is received by the device10 and generates a received signal thereat which the unit 50 rectifiesto provide a potential difference across the lines V−, V+.

After the time T_(a), the capacitor 790 begins to charge through theresistor 780 from the line V+. When the potential across the electrodesof the capacitor 790 exceeds a hysteresis threshold of the gate 750, theoutput of the gate 750 switches from its initial binary state ofsubstantially line V− potential to its other binary state ofsubstantially line V+ potential. Change of output state of the gate 750causes the capacitor 770 to charge through the resistor 760 from theoutput of the gate 750. When the potential across the capacitor 770 issufficient to exceed a hysteresis threshold of a gate in stage 2, thegate in stage 2 switches its output from its initial binary state ofsubstantially line V− potential to its other binary state ofsubstantially line V+ potential. Thus, stage 2 charges its associatedresistor and capacitor which, in turn, trigger stage 3 and so on tostage 8.

Each time a stage is triggered and switches its gate output from itsinitial binary state to its other binary state, anexponentially-decaying current pulse is extracted by the circuit 700from the line V+; current pulses generated by the stages are sensed bythe apparatus 20 which thereby receives information from the device 10incorporating the circuit 700.

Because each stage derives its power directly from the line V+,succeeding stages are not powered through a plurality of precedingstages thereby enable, if required, the circuit 700 to incorporate alarge number of stages, for example in excess of eight stages. Thestages can be microfabricated onto a silicon integrated circuitimplementing timing resistors of each stage, for example the resistor760, as lightly doped polysilicon tracks which can be laser trimmed toprogram data into the circuit 700, for example an identificationsignature code.

In many practical situations, for example where sources of burstinterference are present and interfere with operation of the apparatus20, it is desirable that the circuit 700 is capable of repeatinginformation programmed thereinto whilst radiation is emitted from theapparatus 20 and received by the device 10 incorporating the circuit700. In order to achieve repetition of the information, the circuit 700can be modified into a fifth memory circuit indicated by 800 in FIG. 7.

In FIG. 7, the circuit 800 comprises the circuit 700 shown within adotted line 810 together with an inverting Schmitt gate 820 whose inputis connected to an output of stage 8 and whose output is connected to anend of the resistor 780 formerly connected to the line V+.

When a potential difference is applied between the lines V−, V+, thegate 820 sustains triggering within the circuit 800 so thatexponentially-decaying current pulses are extracted continuously fromthe time V+ and are therefore continuously detectable at the apparatus20.

In a situation where there are present the apparatus 20 and severaldevices each similar to the device 10, there arises a potential problemof contention where several of the devices are triggered simultaneouslyby the apparatus 20. In order to address such contention, the devicescan be modified to assume a form as shown in FIGS. 8 and 9.

In FIG. 8, there is shown a second embodiment of a memory deviceaccording to the invention indicated by 900. The device 900 incorporatesthe substrate 30 and the antenna 40 as included in the device 10. Thedevice 900 further comprises a modified rectification unit and a memoryunit indicated by 910 and 940 respectively. The rectification unit 910comprises the capacitors 52, 56 and the diode 54 together with a seconddiode 920 and a load resistor 930. The capacitors 52, 56 and the diode54 are connected in a similar manner as in the unit 50 to provide thetwo lines V−, V+ from the antenna 40. The diode 920 is connected at itsanode to an anode of the diode 54. Moreover, a cathode of the diode 920is connected to a line D+ and also to a first end of the resistor 930, asecond end of the resistor 930 being connected to the line V−.

In the device 900, the lines V−, V+, D+ are connected to a memory unit940 accommodated in a recess in the substrate 30 at an end of thesubstrate 30 remote from the antenna 40.

In operation, the unit 910 provides a d.c. potential difference acrossthe lines V−, V+ when the device 900 is interrogated by the apparatus20. Moreover, a pulsating unipolar signal is also provided at the D+line with respect to the line V−.

The memory unit 940 incorporates a sixth memory circuit indicated by 950and illustrated in FIG. 9. The circuit 950 comprises the circuit 700included within a dotted line 960 together with an inverting Schmittgate 980, a first and a second MOSFET (FET1, FET2), a resistor R₁ and acapacitor C_(d1), and finally a pulse generator 970. Each of the MOSFETScomprises source and drain electrodes (S₁, S₂) and a gate electrode (G).

In the circuit 950, terminals of the circuit 700 (E₁, E₂) connected tothe line V− in FIG. 7 are summed together and connected to a firstterminal J₁ of the generator 970. The generator 970 is further connectedat its third terminal J₃ to the line V+, and also at its fourth terminalJ₄ to the line V−. Moreover, the generator 970 is connected at itssecond terminal to the gate electrode of MOSFET FET2. The FET2 isconnected at its source electrode S₁ to the line D+.

The FET2 is connected at its drain electrode (S₂) to an input of thegate 980, to a first electrode of the capacitor C₁ and via the resistorR₁ to the drain electrode of the FET1. A second electrode of thecapacitor C₁ is connected to the line V−. Moreover, the source electrodeof the FET1 is connected to the line V+. An output from the gate 980 isconnected to the resistor 780 at an end thereof remote from thecapacitor 790. The gate electrode (G) of the FET1 is connected to theoutput from stage 8 of the circuit 700.

Operation of the circuit 950 incorporated into the device 900interrogated by the apparatus 20 will now be described. When radiationis output from the apparatus 20, it is received at the antenna 40 of thedevice 900. The radiation causes a received signal to be generated atthe antenna 40 which is processed by the rectification unit 910 togenerate a potential difference across the lines V−, V+ and a pulsatingunipolar signal at the line D+ at a frequency of the radiation receivedat the antenna 40. As soon as the potential difference is generatedacross the lines V−, V+, the circuit 950 becomes operational and thecircuit 700 therein becomes triggered; the stages 1 to 8 are triggeredin sequence until stage 8 is triggered and causes the gate electrode (G)of FET1 to be drawn substantially to a potential of the line V+. TheFET1 thereby applies the potential of the line V+ to the resistor R₁which charges the capacitor C₁.

However, charging of the capacitor C₁ is also influenced by chargeinjected or removed therefrom through the FET2 by periodic connection ofthe capacitor C₁ through the FET2 to the line D+. The FET2 is triggeredperiodically by the generator 970 which is triggered each time thecircuit 700 extracts an exponentially decaying current pulse from theline V+. The signal at the line D+ is thus effectively sampled which hasan effect of delaying re-triggering of the circuit 700 after stage 8 hastriggered. Thus, current pulses extracted by the circuit 950 from theline V+ are in bursts punctuated by periods of inactivity. The periodsof inactivity occur even when the apparatus 20 emits radiationcontinuously; the periods of inactivity are asynchronous with respect toother devices responsive to the apparatus 20, thereby providing theapparatus 20 with intervals of time when only one of the devices isresponding to its emitted radiation. The intervals provide the apparatus20 with a method of overcoming contention between a number of devicessimilar to the device 900 operating within interrogation range of theapparatus 20.

Referring back to FIG. 1 and 2, the device 10 with its circuit 200 canbe alternatively implemented using mechanical switching components.Advantages of using mechanical switching components include:

-   -   (a) freedom of latch-up which can affect MOSFET —based circuits        subjected to pulsed high intensity electric fields or ionising        radiation, for example Roentgen-rays or Gamma rays;and    -   (b) an ability to operate at temperatures in excess of 200° C.        where silicon bi-polar and MOSFET semiconductor components can        suffer thermal run-away.

Referring now to FIG. 10, there is shown a seventh memory circuitaccording to the invention indicated by 1100. The circuit 1100 can beincluded in the device 10 by incorporating it into the memory unit 60 insubstitution for the circuit 200.

The circuit 1100 includes a series of stages although only the firstthree stages (stage 1, stage 2, stage 3) of the series are illustratedin the diagram. Each stage includes an elongate piezo-electric bimorphelement, a resistor and a capacitor, for example stage 1 includes apiezo-electric bimorph element 1110, aresistor R₁ and a capacitor C₁.Moreover, the circuit 1100 further includes a resistor R₀ and capacitorC₀ connected to an input of stage 1. Each bimorph element is anchored toa substrate at its first end and capable of flexing at its second endremote from the first end in response to an electric field generatedtransversely through a thickness of the element between its lowersurface and its upper surface. Moreover, each bimorph element comprisesa first upper metallized conductive track running along the length ofthe bimorph on its upper surface, for example a track 1140 of theelement 1110 in stage 1, which is connected to the line V+. Furthermore,each bimorph element comprises a second upper metallized conductivetrack running along the length of the element on its upper surface, forexample a track 1130 of the element 1110 in stage 1, connected to aninput of the bimorph element's associated stage. Each element furtherincludes a third metallized conductive track running along the length ofits lower surface, the third track connected to the line V−; forexample, the bimorph element 1110 of stage 1 includes a metallized track1120 running along the length of its lower surface.

Each stage further comprises a contact point P operable to makeelectrical contact with the first track of the stage's bimorph elementwhen the element flexes at its second end sufficiently in an upwardsdirection towards the point P. Such upward flexing occurs when thesecond track is driven to a positive potential relative to the thirdtrack which is at a potential of the line V−. In each stage, the point Pis connected through the resistor of the stage, for example the resistorR₁ in stage 1, to a first electrode of the capacitor of the stage, forexample the capacitor C₁ of stage 1, and to the output of the stage; asecond electrode of the capacitor is connected to the line V−.

A first end of the resistor R₀ is connected to the line V+. Likewise afirst electrode of the capacitor C₀ is connected to the line V−. Asecond end of the resistor R₀ is connected to a second electrode of thecapacitor C₀ and also connected to the input of stage 1. The output ofstage 1 is connected to the input of stage 2; the output of stage 2 isconnected to the input of stage 3 and so on.

Operation of the circuit 1100 incorporated into the device 10 wheninterrogated by the apparatus 20 will now be described. Initially, theapparatus 20 is not emitting radiation, all the capacitors in thecircuit 1100 are in a discharged state and the bimorph elements of thestages are in a undeflected state where they do not contact onto theirrespective contact points P. At a time Q₁, the apparatus 20 commences toemit radiation which is received at the antenna 40 of the device 10 andcauses a received signal to be generated therein. The unit 50 convertsthe received signal into a potential difference between the lines V−,V+. The circuit 1100 becomes activated by the potential difference whichcauses the capacitor C₀ to charge through the resistor R₀ towards apotential of the line V+. As the capacitor C₀ charges, the bimorphelement 1110 flexes upwardly towards its contact point P to eventuallymake contact therewith, thereby connecting the resistor R₁ to the lineV+. The capacitor C₁ then commences to charge through the resistor R₁towards a potential of the line V+ causing stage 2's bimorph element toflex upwardly and eventual make contact with its associated pointcontact P. Stage 2 then triggers stage 3 which in turn triggers stage 4(not shown) and so on. Each time a bimorph element makes contact withits associated contact point P, an exponentially decaying pulse ofcurrent is extracted from the line V+. Such pulses are sensed by theapparatus 20, the apparatus 20 thereby receiving information from thedevice 10 programmed into the circuit 1100 corresponding to thepropagation delays through the stages.

Each stage can be arranged to exhibit a mutually different propagationdelay therethrough for recording data in the circuit 1100; thepropagation delays can be varied by trimming the resistors in the stagesor modifying the capacitors in the stages or both.

FIG. 11 illustrates a spatial implementation indicated by 1200 of thebimorph elements of stages 1 and 2 in the circuit 1100 shown in FIG. 10.The bimorph elements, for example the element 1110, are each anchored atone of their ends to a substrate 1220. Moreover, each contact point P isimplemented as an overhanging region, for example a region 1210,including an associated contact track, for example a track 1215,operable to contact onto the first track of its associated bimorphelement when it flexes sufficiently. The resistors R₀, R₁, R₂ and thecapacitors C₀, C₁ are located in a region neighbouring to where thebimorph elements are anchored onto the substrate 1220.

Referring now back to FIG. 1, the device 10 includes the loop antenna 40which is effective at receiving incoming radiation by radiation H-fieldcoupling at frequencies lower than around 20 MHz. As radiationfrequencies increase above 20 MHz, the antenna 40 will progressivelyrespond to electric field components of incoming radiation. When theincoming radiation is at a much higher frequency than 20 MHz, forexample in a frequency range of 868 MHz to 2.45 GHz, λ/2 patch antennaeand folded dipole antennae become technically more appropriate. FIG. 12is an illustration of a modified version of the device 10, the modifieddevice indicated generally by 1400. The modified device comprises aninsulating substrate 1410, a metallic film patch antenna 1420 formedonto the substrate 1410, and rectification and memory units 1430, 1440respectively accommodated within recesses formed into the substrate1410. The substrate 1410 is of a size similar to the aforementioned ISOstandard credit card although it can assume other sizes if required. Themodified device 1400, when operable to receive incoming radiation at afrequency of substantially 1 GHz, requires that that the patch antenna1420 is in the order of 2 cm by 3 cm in size, although precisedimensions will depend upon the permittivity of the substrate 1410material.

At relatively higher frequencies in the order of 1 GHz, loading effectsby the modified device 1400 are less noticeable in comparison to thedevice 10 operable to receive and respond to interrogating radiationhaving a carrier frequency of f₀=15 MHz. As a consequence, interrogationequipment interrogating the modified device 1400 needs to becorrespondingly more sensitive. In the modified device 1400, the antenna1420 exhibits an output impedance to the rectification unit 1430 whichis matched thereto. As a consequence, almost all of power conveyed ininterrogating radiation received at the modified device 1400 isrectified in the rectification unit 1430 and supplied as power to thememory unit 1440, the units 1430, 1440 of the modified device 1400 beingof similar design to the units 50, 60 respectively of the device 10.However, the rectification unit 1430 exhibits a radio-frequency load tothe antenna 1420 which is a function of d.c. load presented by thememory device 1440 to the rectification unit 1430. Thus, as electricalload presented by the memory unit 1440 when triggered is a temporalfunction, the rectification unit 1430 responding thereto bycorrespondingly changing its input impedance. Such changes in impedancecause a measurable portion of the interrogating radiation received atthe modified device 1400 to be reflected. Reflected radiation from themodified device 1400 is received by the interrogation equipment whichdetects encoded temporal fluctuations in the reflected radiation bymeasuring phase and amplitude of the reflected radiation with respect tothe interrogating radiation, thereby detecting presence of the modifieddevice 1400.

The aforementioned interrogation equipment will now be further describedwith reference to FIG. 13. The interrogation equipment interrogating thedevice 1400 is indicated generally by 1500. The equipment 1500 comprisesa reference signal generator 1510 for generating a reference signal atan output U₀ of the generator 1510. The output U₀ is connected via apower buffer amplifier 1520 to a transmitter patch antenna 1530, andalso to a signal input of a first signal splitter 1540. The splitter1540 includes two outputs U₁, U₂; in operation, the signal input to thesplitter 1540 is equally coupled to the outputs U₁, U₂, the coupledsignals at the outputs being mutually in phase. The outputs U₁, U₂ arecoupled to first inputs of mixers 1550, 1560 respectively.

The equipment 1500 also includes a receiver patch antenna 1570 whoseoutput is connected via a radio frequency amplifier 1580 to an input ofa second splitter 1590. The second splitter 1590 is implemented as adirectional coupler or, alternatively, as a branch coupler, inoperation, it receives an input signal from the amplifier 1580 andcouples the received signals substantially equally to its two outputsU₄, U₅. A portion of the received signal coupled to the output U₅ isphase shifted by 90°, namely by π/2 radians, relative to a portion ofthe received signal coupled to the output U₄. The outputs U₄, U₅ areconnected to second inputs of the of the mixers 1550, 1560 respectively.Mixer outputs U₆, U₇ of the mixers 1550, 1560 are coupled to inputs I, Qrespectively of a processing unit 1600. The processing unit 1600includes a digital signal processor (DSP) 1610 for receiving signalsinput at the inputs I, Q and operable to measure temporal changes intheir relative phase and relative amplitude corresponding to temporallyencoded reflectivity exhibited by the modified device 1440 and tocross-correlate such temporally encoded reflectivity with code templatesrecorded in the processing unit 1600. The processing unit 1600 furthercomprises an output DET indicative of whether or not the modified device1400 is recognised by the equipment 1500.

Operation of the equipment 1500 in combination with the modified device1400 will now be described with reference to FIGS. 12 and 13. The signalgenerator 1510 generates a reference signal which passes to the bufferamplifier 1520 and is amplified therein to provide an amplifiedreference signal at an output of the amplifier 1520. The amplifiedsignal propagates to the transmitter patch antenna 1530 wherefrom it isemitted as corresponding radiation 1700. The radiation 1700 propagatesto the modified device 1400 and is received at its patch antenna 1420whereat it gives rise to a received signal. The received signal passesto the rectification unit 1430 which rectifies the received signal togenerate a corresponding d.c. potential for energising the memory unit1440. In a similar manner to the aforementioned memory device 10, thememory unit 1440 imposes a temporally encoded fluctuating electricalload to the rectification unit 1430 which in turn temporally modulatesimpedance matching of the rectification unit 1430 to the antenna 1420.As a consequence, a portion 1710 of the radiation 1700 is reflected fromthe antenna 1420 in modulated encoded form to the receiver antenna 1570.The antenna 1570 receives the portion 1710 of the radiation 1700 andgenerates a corresponding received signal at the terminal U₃ whichpropagates to the amplifier 1580 which amplifies it to provide anamplified signal which passes to the input of the splitter 1590. Thesplitter 1590 outputs substantially half of the amplified signal to theoutput U₄ without phase shifting it, and also outputs substantially halfof the amplified signal to the output U₅ phase shifted by 90°, namely inquadrature relative to the signal output at the output U₄. The U₄, U₅output signals pass to the mixers 1550, 1560 respectively whereat thesignals are heterodyned to baseband to corresponding I, Q signals whichpass to the inputs I, Q of the processing unit 1600.

The DSP 1610 receives the I, Q signals input at the inputs I, Q andmeasures temporal changes in their relative phase and relative amplitudecorresponding to temporally encoded reflectivity exhibited by themodified device 1440. The DSP 1610 then cross-correlates the temporalchanges with code templates recorded in the processing unit 1600. If acorrelation is identified by the DSP 1610, the DSP 1610 outputs at itsDET output a code indicative of a modified device 1440 and itsidentification code. Otherwise, if no correlation is identified, the DSP1610 outputs a non-recognition indicative code.

In the modified device 1400, it is desirable that the identificationcode applied by the memory unit 1440 has a clocking rate which is atleast an order of magnitude greater than Doppler frequency shiftsarising from the modified tag 1400 moving relative to the equipment1500, otherwise accurate recognition of codes becomes difficult toexecute reliably in the equipment 1500. Preferably, the memory unit 1440operates to output its associated code at a clocking rate of at least afew kilohertz, for example 50 kHz; such a relatively high clocking rateis advantageous because sequentially triggered switches in the memoryunit 1440 need then only exhibit relatively short associated timeconstants of a few microseconds.

In a situation where there are present the equipment 1500 and severaldevices each similar to the modified device 1400, there arises apotential problem of contention where several of the devices aretriggered simultaneously by the equipment 1500 and the devicessimultaneously reflect encoded radiation back to the equipment 1500. Inorder to address such contention, the devices can be further modifiedwith regard to their associated rectification and memory units 1430,1440 respectively. The rectification unit 1430 in the modified device1440 then assumes a form similar to the rectification unit 910 providingV−, V+ and D+ outputs as illustrated in FIG. 8. Moreover, the memoryunit 1440 is also modified into the form of a memory unit indicated by1800 and illustrated in FIG. 14.

The memory unit 1800 comprises a cascaded series of switches indicatedby 1810 and included within a dashed line 1820. Although three switches1830, 1840, 1850 are shown, the series 1810 can include two or moreswitches depending upon the complexity of signature code desired. Theunit 1800 further comprises a Schmitt inverting gate 1860, anexclusive-OR gate 1870, resistors R₂₀, R₂₁, R₂₂, capacitors C₂₀, C₂₁,C₂₂ and two gating switches 1880, 1890. Each of the switches 1830, 1840,1850 is similar to each of the switches 210 in FIG. 2, or each of theswitches illustrated in FIGS. 4 to 7, 9 to 11; each of the switchesexhibits an associated switching time delay as described above whichcontributes to define a signature code for the device 1400.

Interconnection of parts within the memory unit 1800 will now bedescribed with reference to FIG. 14. The switch 1830 is the first switchin the series 1810, the switch 1830 including an input F₁ connected to afirst end of the resistor R₂₀ and also to a first end of the capacitorC₂₀. A second end of the capacitor C₂₀ is coupled to a signal earth, anda second end of the resistor R₂₀ is connected to an output of theSchmitt gate 1860; the signal earth is connected to the output V− of themodified rectification unit 1430. The switch 1830 further includes anoutput G₁ which is connected to an input F₂ of the switch 1840 andadditionally to a first input of the exclusive-OR gate 1870 and to afirst end of the resistor R₂₁. A second end of the resistor R₂₁ iscoupled to a second input of the exclusive-OR gate 1870 and to a firstend of the capacitor C₂₁, the capacitor C₂₁ having a second end which isconnected to the signal earth. An output G₂ of the switch 1840 iscoupled to an input F₃ of the switch 1850.

An output G₃ of the switch 1850 is connected to a control input K₁ ofthe switch 1880. The input K₁ is operable to control connection betweenterminals K₂ and K₃ of the switch 1880; the terminals K₂, K₃ aremutually isolated through the switch 1880 when the input K₁ is in alogic 0 state, and conversely the terminals K₂, K₃ are mutuallyconnected through the switch 1880 when the input K₁ is in a logic 1state. The terminal K₂ is connected through the resistor R₂₂ to the V+output of the modified rectification unit 1430. The terminal K₃ iscoupled to a terminal K₆ of the switch 1890, to a first end of thecapacitor C₂₂ and to an input of the inverting gate 1860; a second endof the capacitor C₂₂ is connected to the signal earth. A terminal K₅ isconnected to the D+ output of the modified rectification unit 1430.Moreover, an output of the exclusive-OR gate 1870 is connected to acontrol input K₄ of the switch 1890. The input K₄ is operable to controlconnection between terminals K₅ and K₆ of the switch 1880; the terminalsK₂, K₃ are mutually isolated through the switch 1880 when the input K₄is in a logic 0 state, and conversely the terminals K₅, K₆ are mutuallyconnected through the switch 1880 when the input K₄ is in a logic 1state.

The output of the exclusive-OR gate 1870 is at a logic 1 state wheneither of its inputs are set to logic 1, and is at a logic 0 state whenits inputs are both set to a logic 0 state, or alternatively both set toa logic 1 state.

Operation of the memory unit 1800 in combination with the modifiedversion of the rectification unit 1430 and the antenna 1420 will now bedescribed. The equipment 1500 emits the interrogating radiation 1700which is received at the antenna 1420 and generates a correspondingreceived signal there. The received signal passes to the modifiedversion of the rectification unit 1430 and causes a potential differenceto develop between the D+, V+ outputs relative to the V− output. Thepotential difference then activates the memory unit 1800. The capacitorsC₂₀, C₂₁, C₂₂ are initially in a discharged state resulting in theoutput of the gate 1860 being in a logic 1 state; the gate 1860 thereby,through the resistor R₂₀ and the capacitor C₂₀, triggers the series ofswitches 1810 to output their code which modulates load on the output V+and hence modulates radiation reflectivity characteristics of theantenna 1420. Triggering the switch 1830 causes the exclusive-OR gate1870 to connect the D+ output to the capacitor C₂₂ causing it to chargeup towards a logic 1 state. When the series 1810 is triggered through tothe last switch 1856, the output G₃ switches to a logic 1 state whichconnects the V+ output via the resistor R₂₂ to the capacitor C₂₂ causingthe capacitor C₂₂ to further charge towards a logic 1 state. Thecapacitor C₂₂ charges to the logic 1 state causing the output of thegate 1860 to assume a logic 0 state and thereby prevent repetitivetriggering of the series 1810. When a potential difference falls againto a value resulting in the output of the gate 1860 switching to a logic1 state, the series 1810 is then retriggered. Inclusion of the switch1890 enables a potential instantaneously generated at the D+ output tocharge the capacitor C₂₂ and thereby inhibit repetitive triggering ofthe series 1810; the potential at the D+ output is generated if thereare other devices already responding to the interrogating radiation1700. Thus, the circuit 1800 represents a simple approach to resolvingcontention between a number of devices of the invention beinginterrogated simultaneously.

It will be appreciated that modifications can be made to the devices 10,900, 1400 and the circuits 200, 500, 600, 700, 800, 940, 1100 withoutdeparting from the scope of the invention.

For example, the capacitors in the circuits 200, 500, 600, 700, 800,940, 1100 can incorporate liquid crystal material as a dielectrictherein. The liquid crystal material can be made accessible to laserirradiation for changing its state, for example from an isotropic stateto a monotropic state thereby changing the material's dielectricconstant depending upon its state. Thus, use of liquid crystal materialenables the circuits to have data programmed therein by selective laserirradiation. If the liquid crystal material is bistatic, the circuitscan be made re-writeable so that data stored in the devices can beupdated periodically. Moreover, each stage of the circuits 200, 500,600, 700, 800, 940 can be made to function as a local oscillator, forexample by including local regenerative feedback therearound, so thateach stage oscillates briefly when triggered until its succeeding stageis triggered. Such a modification has the advantage that the apparatus20 senses from devices 10, 900 as a sequence of bursts of oscillation ata number of differing frequencies as stages of the devices 10, 900 aresuccessively triggered. The apparatus 20 can thereby demodulateinformation conveyed from the devices using frequency demodulationtechniques.

Furthermore, the circuits 200, 500, 600, 700, 800, 940 can be providedwith current sources at each stage for linearly charging associatedpropagation delay determining capacitors in the stages. As aconsequence, current pulses extracted from the line V+ in operation willbe substantially linearly decaying with time in contrast toexponentially decaying current pulses as in the aforementioned circuits.Use of current sources provides the further advantage that durations ofthe pulses will be less influenced by the magnitude of the potentialdifference generated between the lines V−, V+ when the devices 10, 900are in operation.

1. A memory device operable to receive an input signal and to generatein response a corresponding output signal bearing data, the devicecomprising: a series of circuit stages operable to be triggered by theinput signal at a first stage of the series, thereby causing asequential triggering of the stages along the series to a last stage ofthe series to generate the output signal, the data represented in timedurations taken for each stage in the series to trigger a subsequentstage in the series.
 2. The device according to claim 1, wherein thestages are configured such that each stage incorporates an inputconnected to a preceding stage in the series, and an output connected toa successive stage in the series, each stage being operable to exhibitan associated signal propagation delay therethrough from its input toits output, the propagation delays of the stages being configured torepresent the data.
 3. The device according to claim 1, wherein theseries of stages is configured to sequentially trigger at a rate atleast an order of magnitude greater than Doppler frequency shiftsresulting from relative motion of the device when the output signal isreceived from the device.
 4. The device according to claim 2, wherein astage incorporates a resistor and a capacitor for determining itspropagation delay.
 5. The device according to claim 2, wherein a stageincorporates a capacitor and a current source for determining itspropagation delay, the current source being operable to substantiallylinearly charge its associated capacitor when the stage is triggered. 6.The device according to claim 4, wherein the capacitor includes liquidcrystal material as a dielectric for the capacitor, the material beingoptically modifiable for setting the propagation delay of its associatedstage.
 7. The device according to claim 1, wherein the series of stagesfurther includes a feedback path therearound linking the last stage tothe first stage, the feedback path being operable to cause the series torepetitively output its data during a period when the input signal isapplied to the series.
 8. The device according to claim 7, furthercomprising control circuitry configured to interrupt repetition of thedata in response to the input signal received.
 9. The device accordingto claim 1, wherein a stage is operable to switch its respective outputbetween binary states.
 10. The device according to claim 9, wherein thestage is operable to exhibit a Schmitt-trigger characteristic from itsinput to its output.
 11. The device according to claim 1, furthercomprising coupling circuitry configured to receive input radiation andgenerate the input signal in response, and to receive the output signaland emit output radiation from the coupling circuitry in response. 12.The device to claim 11, wherein the coupling circuitry comprises amagnetically coupled loop antenna configured to receive the inputradiation and emit the output radiation.
 13. The device according toclaim 11, wherein the coupling circuitry comprises a patch antennaconfigured to receive the input radiation and emit the output radiation.14. The device according to claim 11, further comprising convertingcircuitry configured to convert a portion of the input signal into anelectrical signal for powering and triggering the stages, the stagesbeing operable to present a variable load to the electrical signal,thereby modulating a portion of the input radiation reflected from thecoupling circuitry, the portion of the input radiation corresponding tothe output radiation.
 15. The device according to claim 14, wherein theconverting circuitry comprises a rectifier configured to rectify part ofthe input radiation to generate a unipolar signal, and a charge storageconfigured to filter the unipolar signal to generate the electricalsignal.
 16. The device according to claim 1, wherein the stagesincorporate field effect transistors, the stages being coupled togetherby sharing a single field effect transistor drain-source channelextending along the series.
 17. The device according to claim 2, whereina stage incorporates a piezoelectric bimorph switching structureoperable to deflect in response to a signal at the input of the stageand thereby generate a signal at the output of the stage for triggeringa subsequent stage of the series.
 18. The device according to claim 5,wherein the capacitor includes liquid crystal material as a dielectricfor the capacitor, the material being optically modifiable for settingthe propagation delay of its associated stage.
 19. The device accordingto claim 11, wherein the coupling circuitry comprises a folded dipoleantenna configured to receive the input radiation and emit the outputradiation.
 20. A memory device operable to receive an input signal andgenerate an output signal bearing data, the device comprising: a firstcircuit stage configured to receive an input signal and produce a firststage output signal; and a second circuit stage configured to receivethe first stage output signal and produce a second stage output signal,wherein the first circuit stage is triggered to produce the first stageoutput signal after it receives the input signal, and the second circuitstage is triggered to produce the second stage output signal after itreceives the first stage output signal, and wherein the sequentialtriggering of the first and second stages generates a data output, thedata represented in time durations taken for each of the first andsecond stages to produce the first and second stage output signals,respectively.
 21. The device according to claim 20, further comprising:a third circuit stage configured to receive the second stage outputsignal and produce a third stage output signal, wherein the thirdcircuit stage is triggered to produce the third stage output signalafter it receives the second stage output signal, and wherein thesequential triggering of the first, second, and third stages generates adata output, the data represented in time durations taken for each ofthe first, second, and third stages to produce the first, second, andthird stage output signals, respectively.
 22. The device according toclaim 20, further comprising: one or more additional subsequent circuitstages in a series configured to receive a stage output signal from apreceding stage and produce a stage output signal for a successivestage, the first of the additional subsequent stages being configured toreceive the second stage output signal, wherein each of the additionalsubsequent stages is triggered to produce the stage output signal for asuccessive stage after the stage receives the stage output signal from apreceding stage, and wherein the sequential triggering of the stagesgenerates a data output, the data represented in time durations takenfor each of stages to produce the respective stage output signal. 23.The device according to claim 22, wherein the series of stages isconfigured to sequentially trigger at a rate at least an order ofmagnitude greater than Doppler frequency shifts resulting from relativemotion of the device when the data output is received from the device.24. A memory device operable to receive an input signal and generate anoutput signal bearing data, the device comprising: circuit stagesconfigured in a series, wherein a first circuit stage in the series isconfigured to produce an output to a second circuit stage after thefirst circuit stage receives the input signal, wherein commencing withthe second circuit stage in the series, each circuit stage incorporatesan input connected to an output of a preceding stage in the series, eachcircuit stage in the series being configured to produce an output signalat its output after receiving a signal at its input, and wherein eachcircuit stage is operable to exhibit a signal propagation delaytherethrough from its input to its output, the propagation delays of thestages being configured to represent the data, in the output signalbearing data.
 25. The device according to claim 24, wherein a circuitstage incorporates a resistor and a capacitor for determining itspropagation delay.
 26. The device according to claim 25, wherein thecapacitor includes liquid crystal material as a dielectric for thecapacitor, the material being optically modifiable for setting thepropagation delay of its associated circuit stage.
 27. The deviceaccording to claim 24, wherein a circuit stage incorporates a capacitorand a current source for determining its propagation delay, the currentsource being operable to substantially linearly charge its associatedcapacitor when an output of a preceding circuit stage is received. 28.The device according to claim 27, wherein the capacitor includes liquidcrystal material as a dielectric for the capacitor, the material beingoptically modifiable for setting the propagation delay of its associatedstage.
 29. The device according to claim 24, wherein a circuit stageincorporates a piezoelectric bimorph switching structure operable todeflect in response to a signal at the input of the circuit stage andthereby generate a signal at the output of the circuit stage.
 30. Thedevice according to claim 24, further comprising a feedback path linkingthe output of a last circuit stage to the first circuit stage, thefeedback path being operable to cause the circuit stages to repetitivelyproduce the data output during a period when the input signal isreceived by the first circuit stage.
 31. The device according to claim30, further comprising control circuitry configured to interruptrepetition of the data output in response to the input signal received.32. The device according to claim 24, further comprising couplingcircuitry configured to receive input radiation and generate the inputsignal in response, and to receive the data output and emit outputradiation from the coupling circuitry in response.
 33. The deviceaccording to claim 32, further comprising converting circuitryconfigured to convert a portion of the input signal into an electricalsignal for powering and providing input to the circuit stages, thecircuit stages being operable to present a variable load to theelectrical signal, thereby modulating a portion of the input radiationthat is reflected from the coupling circuitry, the portion of the inputradiation corresponding to the output radiation.
 34. The deviceaccording to claim 33, wherein the converting circuitry comprises arectifier configured to rectify part of the input radiation to generatea unipolar signal, and a charge storage configured to filter theunipolar signal to generate the electrical signal.
 35. The deviceaccording to claim 22, wherein the circuit stages incorporate fieldeffect transistors, the circuit stages being coupled together by sharinga single field effect transistor drain-source channel extending alongthe circuit stages.
 36. The device according to claim 8, wherein thecontrol circuitry includes a pulse generator configured to cause aswitch to couple an electrical signal to the feedback path to affect thecharging of a capacitor on the feedback path capable of triggering thefirst stage of the series of stages.
 37. The device according to claim17, wherein the piezoelectric bimorph switching structure includes afirst and second conductive track on an upper surface and a thirdconductive track on a lower surface, wherein the switching structure isoperable to deflect based on a potential between the second and thirdtrack, thereby causing the first track to make an electrical contactthat causes a subsequent stage in the series to be triggered.
 38. Thedevice according to claim 1, wherein the stages are operable to presenta variable load to an electrical signal as each stage is triggered andthereby generate the output signal bearing data.
 39. The deviceaccording to claim 20, wherein the circuit stages are operable topresent a variable load to an electrical signal as each circuit stage istriggered and thereby generate the output signal bearing data.
 40. Thedevice according to claim 20, wherein a circuit stage incorporates aresistor and a capacitor for determining the time duration taken toproduce its circuit stage output signal.
 41. The device according toclaim 20, wherein a circuit stage incorporates a capacitor and a currentsource for determining the time duration taken to produce its circuitstage output signal, the current source being operable to substantiallylinearly charge its associated capacitor when the circuit stage istriggered.
 42. The device according to claim 22, wherein the series ofcircuit stages further includes a feedback path therearound linking thelast stage to the first stage, the feedback path being operable to causethe series to repetitively output its data during a period when theinput signal is applied to the series.
 43. The device according to claim42, further comprising control circuitry configured to interruptrepetition of the data in response to the input signal received.
 44. Thedevice according to claim 43, wherein the control circuitry includes apulse generator configured to cause a switch to couple an electricalsignal to the feedback path to affect the charging of a capacitor on thefeedback path capable of triggering the first stage of the series ofcircuit stages.
 45. The device according to claim 20, wherein a circuitstage is operable to switch its respective output between binary states.46. The device according to claim 45, wherein the circuit stage isoperable to exhibit a Schmitt-trigger characteristic from its input toits output.
 47. The device according to claim 20, wherein a circuitstage incorporates a piezoelectric bimorph switching structure operableto deflect in response to a signal at the input of the stage and therebygenerate a signal at the output of the stage.
 48. The device accordingto claim 47, wherein the piezoelectric bimorph switching structureincludes a first and second conductive track on an upper surface and athird conductive track on a lower surface, wherein the switchingstructure is operable to deflect based on a potential between the secondand third track, thereby causing the first track to make an electricalcontact that causes a subsequent stage in the series to be triggered.49. The device according to claim 24, wherein the circuit stages areconfigured to sequentially produce an output to a subsequent stage at arate at least an order of magnitude greater than Doppler frequencyshifts resulting from relative motion of the device when the outputsignal bearing data is received from the device.
 50. The deviceaccording to claim 24, wherein a circuit stage is operable to switch itsrespective output between binary states.
 51. The device according toclaim 50, wherein the circuit stage is operable to exhibit aSchmitt-trigger characteristic from its input to its output.
 52. Thedevice according to claim 24, wherein the circuit stages incorporatefield effect transistors, the stages being coupled together by sharing asingle field effect transistor drain-source channel extending along theseries of stages.
 53. The device according to claim 24, wherein thecircuit stages are operable to present a variable load to an electricalsignal as each circuit stage is caused to produce an output signal to asubsequent stage and thereby generate the output signal bearing data.54. The device according to claim 29, wherein the piezoelectric bimorphswitching structure includes a first and second conductive track on anupper surface and a third conductive track on a lower surface, whereinthe switching structure is operable to deflect based on a potentialbetween the second and third track, thereby causing the first track tomake an electrical contact that causes the signal to be generated at theoutput of the stage.
 55. The device according to claim 31, wherein thecontrol circuitry includes a pulse generator configured to cause aswitch to couple an electrical signal to the feedback path to affect thecharging of a capacitor on the feedback path capable of causing thefirst circuit stage to produce an output to the second circuit stage.